In the field of computer design, a target which is sought continuously by people is to lower power from chip level to system level. With power consumption increased, cost for power supply and cooling of a system is increased in a higher speed.
Power of a computer system includes core power and I/O (Input/Output) power. At present, there are a lot of methods for lowering power of the computer system, for example:
Chip level: designing or selecting a low power chipsets;
System level: dynamically lowering operation voltage and operation frequency through DVFS (Dynamic Voltage and Frequency Scaling);
Compiler level: selecting lower power instructions;
OS (Operating System) level: disabling some function units when a system is not utilized through task scheduling;
Network level: switching to a waiting or suspended mode when NIC (Network Interface Card) doesn't work.
A specific example is a power management system of Intel DBS (Demand Based Switching), which has a logic for adjusting core power. It can adjust core voltage based on CPU's workload. The detailed description about Intel DBS can be seen in the Intel white paper: Addressing Power and Thermal Challenges in the Datacenter, www.intel.com/products/services/intelsolutionservices/success/techdocs/wp/thermal.pdf. However, the power management system of Intel DBS is mainly focused on the processor itself and doesn't lower I/O power effectively.
For example, it is reported in the article “Low Power Address Encoding using Self-Organizing Lists” written by Mahesh Mamidipaka, Dan Hirschberg and Nikil Dutt, Proceedings of the 2001 International Symposium on Low Power Electronics and Design (ISLPED '01), that, for the system optimized to low power, the proportion of I/O power and total power is between 10% and 80%, and generally 50%.
Thereby, it is required to lower I/O power of a computer system at the same time of lowering core power of the computer system.
A method for lowering I/O power of a computer system is disclosed in the article “Dynamic Coding Technique For Low-Power Data Bus” written by M. Madhu, V. Srinivasa and V. Kamakoti, Proceeding of the IEEE Computer Society Annual Symposium on VLSI, 2003, which is characterized in that, a code with a minimum hamming distance, which is calculated based on character distribution of the former data and the current data, is used to be transferred. Thus it can be seen that, this method is required to adopt a dynamic encoding scheme to encode data, and monitor and compare the former data and the current data in real time, so the spending is big, and the efficiency is low.
Thereby, there is required a method for lowering I/O power of a computer system effectively.